sp5769 3ghz i 2 c bus synthesiser november 2004 features complete 3? ghz single chip system optimised for low phase noise, with comparison frequencies up to 4 mhz no rf prescaler selectable reference division ratio selectable reference/comparison frequency output selectable charge pump current with 10:1 ratio four selectable i 2 c addresses ? 2 c fast mode compliant with 3?v and 5v logic levels four switching ports functional replacement for sp5659 (except adc) pin compatible with sp5655 power consumption 138mw with v cc = 5?v, all ports off esd protection 2kv min., mil-std-883b method 3015 cat.1 (normal esd handling procedures should be observed) applications digital satellite and cable tuning systems communications systems description the sp5769 is a single chip frequency synthesiser designed for tuning systems up to 3ghz. the rf preamplifier interfaces direct with the rf programmable divider, which is of mn1a construction so giving a step size equal to the loop comparison frequency and no prescaler phase noise degradation over the full rf operating range. the comparison frequency is obtained either from an on-chip crystal controlled oscillator, or from an external source. the oscillator frequency, f ref , or phase comparator frequency, f comp , can be switched to the ref/ comp output providing a reference for a second frequency synthesiser. the synthesiser is controlled via an 1 2 c bus and is fast mode compliant. it can be hard wired to respond to one of four addresses to enable two or more synthesisers to be used on a common bus. the device contains four switching ports p0 - p3. 4-bit latch and port interface 4 16/17 4-bit count 11-bit count 15-bit latch reference divider ref/comp crystal cap crystal charge pump drive i 2 c bus transceiver address sda scl rf input p3 11 2 3 1 16 6 13 14 10 4 5 pump 2 bit 4 bit 2 bit 3 bit 789 p2 p1 p0 cp test mode set lock f pd /2 f pd /2 select enable/ select figure 1 - sp5769 block diagram absolute maximum ratings all voltages are referred to v ee = 0v supply voltage, v cc rf differential input voltage all i/o port dc offsets sda and scl dc offset storage temperature junction temperature mp16 thermal resistance chip to ambient, ja chip to case, jc -3v to + 7v 2?vp-p -0? to v cc +0?v 20? to 6v - 5 5 c to + 12 5 c + 15 0 c 80 c/w 20 c/w ordering information sp5769a/kg/mp2s 16 pin soic* tubes sp5769a/kg/qp1t 16 pin qsop tape & reel sp5769a/kg/mp1s 16 pin soic tubes sp5769a/kg/mp2t 16 pin soic* tape & reel sp5769a/kg/qp2t 16 pin qsop* tape & reel sp5769a/kg/qp1s 16 pin qsop tubes sp5769a/kg/mp1t 16 pin soic tape & reel sp5769a/kg/qp2s 16 pin qsop* tubes *pb free matte tin zarlink sem iconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2002-2004, zarlink semiconductor inc. all rights reserved.
2 sp5769 figure 2 - pin connections - top view mp16 sp 5769 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 charge pump crystal cap crystal sda scl port p3/loglev port p2 port p1 drive v ee rf input rfinput v cc ref/comp address portp0 qp16 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 sp 5769 charge pump crystal cap crystal sda scl port p3/loglev port p2 port p1 drive v ee rf input rfinput v cc ref/comp address portp0 electrical characteristics test conditions (unless otherwise stated): t amb = - 4 0 c to + 8 0 c, v cc = + 45v to + 55 v . these characteristics are guaranteed by either production test or design. they apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. characteristic conditions max. min. value typ. units 100mhz to 200mhz, see figure 3 200mhz to 3ghz, see figure 3 see figure 4 5v i 2 c logic selected 33v i 2 c logic selected 5v i 2 c logic selected 33v i 2 c logic selected input voltage = v cc input voltage = v ee v cc = v ee i sink = 3ma i sink = 6ma see table 6, v pin1 = 2v v pin1 = 2v, v cc = 150v, t amb = 25 c v pin16 = 07v see figure 5 for application sinewave coupled via 10nf blocking capacitor sinewave coupled via 10nf blocking capacitor ac coupled, see note 2 00625 to 20mhz enabled by bit re = 1 ssb, within loop bandwidth, all comparison frequencies see table 1 pin 25 300 300 55 55 15 1 10 - 10 10 04 06 400 + - 10 20 20 05 4 32767 supply current rf input input voltage input impedance sda, scl input high voltage input low voltage input high current input low current leakage current input hysteresis sda output voltage scl clock rate charge pump output current output leakage drive output current crystal frequency external reference input frequency drive level buffered ref/comp output amplitude output impedance comparison frequency equivalent phase noise at phase detector rf division ratio reference division ratio 12 13,14 4,5 4 5 1 1 16 2,3 3 11 100 40 3 23 0 0 04 05 2 2 02 - 148 240 20 63 035 250 ma mvrms mvrms v v v v a a a v v v khz na ma mhz mhz vp-p vp-p mhz dbc/hz cont
3 sp5769 functional description the sp5769 contains all the elements necessary, with the exception of a frequency reference, loop filter and external high voltage transistor, to control a varactor tuned local oscillator, so forming a complete pll frequency synthesised source. the device allows for operation with a high comparison frequency and is fabricated in high speed logic, which enables the generation of a loop with good phase noise performance. the rf input signal is fed to an internal preamplifier, which provides gain and reverse isolation from the divider signals. the output of the preamplifier interfaces with the 15-bit fully programmable divider which is of mn1a architecture, where the dual modulus prescaler is 416/ 17, the a counter is 4 bits, and the m counter is 11 bits. the output of the programmable divider is applied to the phase comparator where it is compared in both phase and frequency domains with the comparison frequency. this frequency is derived either from the on-chip crystal controlled oscillator or from an external reference source. in both cases the reference frequency is divided down to the comparison frequency by the reference divider which is programmable into 1 of 16 ratios as detailed intable 1. the output of the phase detector feeds a charge pump and loop amplifier section, which when used with an external high voltage transistor and loop filter, integrates the current pulses into the varactor line voltage. the programmable divider output f pd /2 can be switched to port p0 by programming the device into test mode. the test modes are described intable 5. programming the sp5769 is controlled by an i 2 c data bus and is compatible with both standard and fast mode formats and with i 2 c data generated from nominal 33v and 5v sources. the i 2 c logic level is selected by the bi-directional port p3/ loglev. 5v logic levels are selected by connecting p3/ loglev to v cc or leaving it open circuit; 33v logic levels are set by connecting p3/loglev to ground. if this port is used as an input the p3 data should be programmed to high impedance. if used as an output only 5v logic levels can be used, in which case the logic state imposed by the port on the input is ignored. data and clock are fed in on the sda and scl lines respectively as defined by i 2 c bus format . the synthesiser can either accept data (write mode), or send data (read mode). the lsb of the address byte (r/w) sets the device into write mode if it is low, and read mode if it is high. tables 2 and 3 illustrate the format of the data. the device can be programmed to respond to several addresses, which enables the use of more than one synthesiser in an i 2 c bus system. table 4 shows how the address is selected by applying a voltage to the address input. when the device receives a valid address byte, it pulls the sda line low during the acknowledge period, and during following acknowledge periods after further data bytes are received. when the device is programmed into read mode, the controller accepting the data must be pulled low during all status byte acknowledge periods to read another status byte. if the controller fails to pull the sda line low during this period, the device generates an internal stop condition, which inhibits further reading. electrical characteristics (continued) 2 3 0 characteristic v port = 07v v port = v cc see note 1 see table 4 v in = v cc v in = v ee see note 3 5v i 2 c logic level selected or open circuit 33v i 2 c logic level selected v in = v ee to v cc conditions max. min. value units ma a ma a v v a typ. 10 1 - 05 15 10 output ports p3 - p0 sink current leakage current address select input high current input low current logic level select input high level input low level input current pin 6-9 10 6 notes 1. output ports high impedance on power-up, with sda and scl at logic ?0?. 2. if the ref/comp output is not used, the output should be left open circuit or connected to v cc and disabled by setting re = ?0?. 3. bi-dectional port. when used as an output, the input logic state is ignored. when used as an input, the port should be switch ed into high impedance (off) state.
4 sp5769 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 r3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 r2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 r1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 r0 division ratio 2 4 8 16 32 64 128 256 24 5 10 20 40 80 160 320 a byte transmission, the previous byte data is retained. to facilitate smooth fine tuning, the frequency data bytes are only accepted by the device after all 15 bits of frequency data have been received, or after the generation of a stop condition. read mode when the device is in read mode, the status byte read from the device takes the form shown in table 3. bit 1 (por) is the power-on reset indicator, and this is set to a logic ?1? if the v cc supply to the device has dropped below 3v (at 25 c ), e.g. when the device is initially turned on. the por is reset to ?0? when the read sequence is terminated by a stop command. when por is set high this indicates the programmed information may be corrupted and the device reset to power up condition. bit 2 (fl) indicates whether the device is phase locked, a logic?1?is present if the device is locked, and a logic ?0? if it is not. programable features rf programmable divider function as described above. reference programmable divider function as described above. charge pump current the charge pump current can be programmed by bits c1 and c0 within data byte 5, as defined in table 6. test mode the test modes are invoked by setting bit t2 = 1, with selected test modes as defined by bits t1 and t0 as described in table 5. clock input on crystal and rf input pins are required to invoke fl test modes. reference/comparison frequency output the reference frequency f ref or comparison frequency f comp can be switched to the ref/comp output, function as defined in table 7. re and rs default to logic?1?during device power up, thus enabling the comparison frequency f comp at the ref/comp output. write mode with reference to table 2, bytes 2 and 3 contain frequency information bits 2 14 -2 0 inclusive. bytes 4 and 5 control the reference divider ratio (see table 1), charge pump setting (see table 6), ref/comp output (see table 7), output ports and test modes (see table 5). after reception and acknowledgement of a correct address (byte 1), the first bit of the following byte determines whether the byte is interpreted as a byte 2 or 4, a logic ?0? indicating byte 2, and a logic ?1? indicating byte 4. having interpreted this byte as either byte 2 or 4, the following data byte will be interpreted as byte 3 or 5 respectively. having received two complete data bytes, additional data bytes can be entered, where byte interpretation follows the same procedure, without re- addressing the device. this procedure continues until a stop condition is received. the stop condition can be generated after any data byte, if however it occurs during table 1 - reference division ratios address programmable divider programmable divider control data control data 1 0 2 7 1 c1 byte 1 byte 2 byte 3 byte 4 byte 5 1 2 14 2 6 t2 c0 0 2 13 2 5 t1 re 0 2 12 2 4 t0 rs 0 2 11 2 3 r3 p3 ma1 2 10 2 2 r2 p2 ma0 2 9 2 1 r1 p1 0 2 8 2 0 r0 p0 a a a a a table 2 write data format (msb transmitted first) msb lsb a acknowledge bit ma1, ma0 variable address bits (see table 4) 2 14 -2 0 programmable division ratio control bits r3-r0 reference division ratio select (see table 1) c1, c0 charge pump current select (see table 6) re reference oscillator output enable rs ref/comp output select when re=1 (see table 7) t2-t0 test mode control bits (see table 5) p3-p0 p3, p2, p1 and p0 port output states
5 sp5769 a acknowledge bit ma1, ma0 variable address bits (see table 4) por power on reset indicator fl phase lock flag address status byte 1 por byte 1 byte 2 1 fl 0 0 0 0 0 0 ma1 0 ma0 0 1 0 a a msb lsb table 3 - read data format (msb transmitted first) 100 1000 2000 frequency (mhz) vin (mvrms into 50 ) 300 40 200 operating window 3000 4000 100 figure 3 - typical rf input sensitivity table 4 - address selection * programmed by connecting a 15k resistor from pin 10 to v cc 0 0 1 1 ma1 0 to 01v cc open circuit 04v cc to 06v cc * 09v cc to v cc address input voltage level ma0 0 1 0 1 t2 test mode description 0 1 1 1 1 t1 x 0 0 1 1 t0 x 0 1 0 1 normal operation charge pump sink status byte fl = logic ?0? charge pump source status byte fl = logic ?0? charge pump disable status byte fl = logic ?1? p0 = f pd /2 table 5 - test modes 0 1 1 re high impedance f ref selected f comp selected ref/comp output rs x 0 1 table 7 - ref/comp output current ( a) 0 0 1 1 0 1 0 1 c1 c0 min. typ. max. + - 1 1 6 + - 247 +- 517 +- 1087 + - 155 + - 330 + - 690 + - 1450 +- 194 +- 412 +- 862 +- 1812 table 6 - charge pump current
6 sp5769 table 8 - component values for figure 6 j2 j1 j0.5 j0.2 0 j0.2 j0.5 j1 j2 1 0.5 0.2 j5 j5 2 5 05ghz 1ghz 25ghz 15ghz s11: z o = 50 normalised to 50 figure 4 - rf input impedance figure 5 - crystal oscillator application 150p 68p sp5769 2 3 c22 c23 c24 led 1 led 2 r1 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 s1 t1 vco x1 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 c19 c20 c21 component 18pf 22nf 68pf 1nf 1nf 10nf 100nf 47 f 100nf 100pf 1nf 100pf 100pf 47nf 100pf 47 f 10nf 39pf 100pf 1nf 1nf value/type component 100pf 47 f 1nf hlmpk-150 hlmpk-150 47k 47k 47k 47k 133k 22k 1k 0 16 16 16 68 sw dip-2 bcw31 pos_2000 4mhz value/type
7 sp5769 figure 6 - sp5769 evaluation board sda5 5v scl5 c3 r7 c2 c5 c4 v cc r8 30v t1 r9 r10 c14 rf3 comp output rf2 ext ref s1 r1 r4 8v led1 led2 c10 c17 r11 r12 r13 c20 8v rf input rf1 c19 c21 r14 vco rf out vt 1 2 j2 varactor c15 c13 c12 j5 3 4 5 6 1 2 3 4 5 8v c8 c9 30v c16 c7 5v v cc j1 power connector 1 port outputs j4 vco tuning range = 1370mhz to 2000mhz c18 x1 c1 c6 sp 5769 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v cc r5 r6 led3 led4 lk1 2 3 4 add con1 c23 c22 c24
8 sp5769 top view bottom view figure 7 - sp5769 evaluation board layout
www.zarlink.com information relating to products and services furnished herein by zarlink semiconductor inc. or its subsidiaries (collectively ?zarlink?) is believed to be reliable. however, zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from t he application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of product or service conveys any license, either express or implied, u nder patents or other intellectual property rights owned by zarlink or licensed from third parties by zarlink, whatsoever. purchasers of products are also hereby notified that the use of product in certain ways or in combination with zarlink, or non-zarlink furnished goods or services may infringe patents or other intellect ual property rights owned by zarlink. this publication is issued to provide information only and (unless agreed by zarlink in writing) may not be used, applied or re produced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, t heir specifications, services and other information appearing in this publication are subject to change by zarlink without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user?s responsibility t o fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not b een superseded. manufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. all products and materials are sold and services provided subject to zarlink?s conditi ons of sale which are available on request. purchase of zarlink?s i 2 c components conveys a licence under the philips i 2 c patent rights to use these components in and i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright zarlink semiconductor inc. all rights reserved. technical documentation - not for resale for more information about all zarlink products visit our web site at
|
